1. Field of Invention
This invention relates generally to phase locked oscillators and more particularly to improvements therein for reducing the cost and complexity of such devices adapted primarily for use in data processing applications.
2. Description of Prior Art
The use of phase locked oscillators in digital data processing systems is well known to those skilled in the art. In such systems the phase locked oscillator serves to track input data pulses, supplied for example from a magnetic read head, for the purpose of recovering recorded data. It is generally desired that the data bits be recorded as densely as possible in the interest of increasing the storage capacity of the recording media. As a consequence of this dense storage or high packing density, the read pulses representative of the respective data bits may be shifted from their appropriate positions relative to one another. Bit shift is caused by an interaction of each read pulse with adjacent read pulses. The amount of bit shift which may occur is dependent on the packing density and the data pattern. In the case of a data pattern where the pulses are uniformly or periodically spaced from one another, the bit shift, if any, is usually inconsequential. On the other hand, where the data pattern is nonuniform or aperiodic, the individual pulses are shifted in proportion to both the nominal spacing between pulses and the difference in spacing of each pulse from the immediately adjacent pulses on each side thereof with the bit shift being greater for relatively closely spaced pulses and less for relatively widely spaced pulses having the same space differential.
In recognition of the bit shift problem, the development of the magnetic data recording and recovery art has been concerned with the generation of encoding techniques which not only reduce the bit shift but also afford self-clocking for eliminating the need for a separate clock track on the recording medium. NRZ code, for example, which is characterized by a change from one signal level to another on the occurrence of a one data bit following a zero data bit and by a change back to the original signal level when a zero follows a one, is not capable of selfclocking because of the long interval which exists between signal transitions for a succession of either ones or zeros. Phase modulation (PM) code, which is characterized by a signal transition in one direction for a one bit and a signal transition in the opposite direction for a zero bit, assures the frequent occurrence of signal transitions and therefore is capable of self-clocking. However, signal transitions are also required between ones and zeros to assure that the one and zero signal transitions are made in the proper direction. The need for these additional transitions intermediate the data bit transitions aggravates the bit shift problem. Frequency modulation (FM) code is characterized by advantages and limitations similar to those of PM code. Another encoding technique commonly known as modified frequency modulation (MFM) eliminates the transitions between data bits and also avoids long intervals without any transitions, thereby affording the advantages of both high packing density and self-clocking. A variation of the MFM code known as doubly modified frequency modulation (M.sup.2 FM) also affords both of these advantages and is preferred for one reason or another in some instances.
In both MFM and M.sup.2 FM encoded systems, one bits are recorded and reproduced at one time in a bit cell or interval, for instance, at the center thereof while zero bits are recorded and reproduced in accordance with specific encoding rules so as to occur at another time in the bit cell, for instance, at the leading or trailing edge. The specific encoding rules determine those zeros which are recorded and those which are not recorded. In other words, zeros are recorded only as necessary to achieve self-clocking. Upon read-out from the recording medium, both the ones and the recorded zeros are reproduced, so the data recovery apparatus must operate in a manner to respond to the reproduced ones and disregard the reproduced zeros.
The present invention will be described in relation to recovery of M.sup.2 FM encoded data which will be explained subsequently in greater detail by reference to the drawings provided herewith for use in conjunction with the description of the preferred embodiment. In any event, from the foregoing comments concerning bit shift and a scrutiny of the accompanying drawings, it will be appreciated, as is indeed the case, that one bits of M.sup.2 FM code tend to be shifted more than zero bits. This characteristic of the bit shift of M.sup.2 FM encoded data can be used to advantage for enhancing data recovery.
In a data recovery system employing a phase locked oscillator, the oscillator functions to provide a reference signal which is fed back for phase comparison with an input signal representative of the input data bits to control the frequency of the oscillator such that it tracks the input signal. The oscillator thus inherently generates a data recovery gating signal. This gating signal is typically symmetrical, that is, it has a fifty percent duty cycle so it is at one level half the time in each cycle for gating or recovering one bits and is at another level for the remainder of each cycle during the time when zero bits may be present. By the use of appropriate logic circuits responsive to the gating signal, zero bits are blocked so that the recovered signal is representative only of the one bits present in the originally recorded data pattern. In the case of M.sup.2 FM code where it is known that one bits tend to be shifted more than zero bits, it has been recognized that data recovery can be improved by allocating more than fifty percent of the data recovery gating signal cycle to recovery of one bits and proportionately less to the interval in which zero bits may be present. This is accomplished by the provision of an asymmetrical data recovery gating signal. Heretofore, systems operating in this fashion have been constructed with analog circuits coupled in the phase locked oscillator feedback path comprising the connection between the output of the oscillator and the input of the phase comparator with the attendant requirement for precision components to achieve desired accurracy, thereby making the systems complex and expensive to produce and maintain.
In accordance with the principles of the present invention, a phase locked oscillator is provided comprising digital components for producing the phase comparator reference signal and asymmetrical data recovery signal. The digital circuit component construction of the feedback path in accordance with the teaching of the instant invention significantly reduces system complexity with a concomitant reduction in manufacturing and maintenance costs.